SH7080 Datasheet, PDF (745/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
5, 4 POE2M[1:0] 00
R/W*² POE2 mode 1, 0
These bits select the input mode of the POE2 pin.
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE2 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE2 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
3, 2 POE1M[1:0] 00
R/W*² POE1 mode 1, 0
These bits select the input mode of the POE1 pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
1, 0 POE0M[1:0] 00
R/W*² POE0 mode 1, 0
These bits select the input mode of the POE0 pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE0 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE0 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Rev. 3.00 May 17, 2007 Page 687 of 1582
REJ09B0181-0300