SH7080 Datasheet, PDF (104/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
DMULU.L Rm,Rn
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
0011nnnnmmmm0101 2 to 5*
DT
Rn
Rn - 1 → Rn, if Rn = 0, 1 → 0100nnnn00010000 1
T, else 0 → T
EXTS.B Rm,Rn
A byte in Rm is sign-
extended → Rn
0110nnnnmmmm1110 1
EXTS.W Rm,Rn
A word in Rm is sign-
extended → Rn
0110nnnnmmmm1111 1
EXTU.B Rm,Rn
A byte in Rm is zero-
extended → Rn
0110nnnnmmmm1100 1
EXTU.W Rm,Rn
A word in Rm is zero-
extended → Rn
0110nnnnmmmm1101 1
MAC.L
@Rm+,@Rn+
Signed operation of (Rn)
× (Rm) + MAC → MAC,
32 × 32 + 64 → 64 bits
0000nnnnmmmm1111 2 to 5*
MAC.W
@Rm+,@Rn+
Signed operation of (Rn)
× (Rm) + MAC → MAC,
16 × 16 + 64 → 64 bits
0100nnnnmmmm1111 2 to 4*
MUL.L Rm,Rn
Rn × Rm → MACL
32 × 32 → 32 bits
0000nnnnmmmm0111 2 to 5*
MULS.W Rm,Rn
Signed operation of Rn
× Rm → MAC
16 × 16 → 32 bits
0010nnnnmmmm1111 1 to 3*
MULU.W Rm,Rn
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32 bits
0010nnnnmmmm1110 1 to 3*
NEG Rm,Rn
0-Rm → Rn
0110nnnnmmmm1011 1
NEGC Rm,Rn
0-Rm-T → Rn,
Borrow → T
0110nnnnmmmm1010 1
SUB Rm,Rn
Rn-Rm → Rn
0011nnnnmmmm1000 1
SUBC Rm,Rn
Rn-Rm–T → Rn,
Borrow → T
0011nnnnmmmm1010 1
SUBV Rm,Rn
Rn-Rm → Rn,
Underflow → T
0011nnnnmmmm1011 1
Note: * Indicates the number of execution cycles for normal operation.
T Bit
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Comparison
result
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Borrow
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Borrow
Overflow
Rev. 3.00 May 17, 2007 Page 46 of 1582
REJ09B0181-0300