SH7080 Datasheet, PDF (131/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Table 4.4 Frequency Division Ratios Specifiable with FRQCR
PLL
Multipli-
FRQCR Division Ratio
Setting
cation
Ratio Iφ Bφ Pφ MIφ MPφ Iφ
×8
1/8 1/8 1/8 1/8 1/8 1
1/4 1/8 1/8 1/8 1/8 2
1/4 1/8 1/8 1/4 1/8 2
1/4 1/4 1/8 1/8 1/8 2
1/4 1/4 1/8 1/4 1/8 2
1/4 1/4 1/8 1/4 1/4 2
1/4 1/4 1/4 1/4 1/4 2
1/3 1/3 1/3 1/3 1/3 8/3
1/2 1/8 1/8 1/8 1/8 4
1/2 1/8 1/8 1/4 1/8 4
1/2 1/8 1/8 1/2 1/8 4
1/2 1/4 1/8 1/8 1/8 4
1/2 1/4 1/8 1/4 1/8 4
1/2 1/4 1/8 1/4 1/4 4
1/2 1/4 1/8 1/2 1/8 4
1/2 1/4 1/8 1/2 1/4 4
1/2 1/4 1/4 1/4 1/4 4
1/2 1/4 1/4 1/2 1/4 4
1/2 1/2 1/8 1/8 1/8 4
1/2 1/2 1/8 1/4 1/8 4
1/2 1/2 1/8 1/4 1/4 4
1/2 1/2 1/8 1/2 1/8 4
1/2 1/2 1/8 1/2 1/4 4
1/2 1/2 1/8 1/2 1/2 4
1/2 1/2 1/4 1/4 1/4 4
1/2 1/2 1/4 1/2 1/4 4
1/2 1/2 1/4 1/2 1/2 4
Clock Ratio
Clock Frequency (MHz)*
Input
Bφ Pφ MIφ MPφ Clock Iφ
Bφ Pφ MIφ MPφ
1 1 1 1 10
10 10 10 10 10
1111
20 10 10 10 10
1121
20 10 10 20 10
2111
20 20 10 10 10
2121
20 20 10 20 10
2122
20 20 10 20 20
2222
20 20 20 20 20
8/3 8/3 8/3 8/3
26 26 26 26 26
1111
40 10 10 10 10
1121
40 10 10 20 10
1141
40 10 10 40 10
2111
40 20 10 10 10
2121
40 20 10 20 10
2122
40 20 10 20 20
2141
40 20 10 40 10
2142
40 20 10 40 20
2222
40 20 20 20 20
2242
40 20 20 40 20
4111
40 40 10 10 10
4121
40 40 10 20 10
4122
40 40 10 20 20
4141
40 40 10 40 10
4142
40 40 10 40 20
4144
40 40 10 40 40
4222
40 40 20 20 20
4242
40 40 20 40 20
4244
40 40 20 40 40
Rev. 3.00 May 17, 2007 Page 73 of 1582
REJ09B0181-0300