SH7080 Datasheet, PDF (416/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
A. Insert one idle cycle to access the interface other than the SDRAM interface after the write
access cycle is performed in the SDRAM interface.
B. Insert one idle cycle to access the SDRAM interface after the normal space interface with
the external wait invalidated or the byte-selection SRAM interface with the BAS bit = 0
specified is accessed.
C. Insert one idle cycle to access the SDRAM interface after the MPX-I/O interface is
accessed.
D. Insert two idle cycles to access the MPX-I/O interface from the external bus that is in the
idle status.
E. Insert one idle cycle to access the MPX-I/O interface after a read cycle is performed in the
normal space interface, byte-selection SRAM interface with the BAS bit = 0, and the
SDRAM interface.
F. Insert two idle cycles to access the MPX-I/O interface after a write cycle is performed in
the SDRAM interface.
Tables 9.29 to 9.34 list the minimum number of idle cycles to be inserted for the normal space
interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the
number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS.
Rev. 3.00 May 17, 2007 Page 358 of 1582
REJ09B0181-0300