SH7080 Datasheet, PDF (1036/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Compare Match Timer (CMT)
Initial
Bit
Bit Name value R/W Description
15 to 8 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/(W)*¹ Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing conditions]
• When 0 is written to this bit after reading CMF=1*²
• When CMT registers are accessed when the value
of the DISEL bit of MRB in the DTC is 0 after
activating the DTC by CMI interrupts.
[Setting condition]
1: CMCNT and CMCOR values match
6
CMIE
0
R/W Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF=1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
5 to 2 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0
CKS[1:0] 00
R/W Clock Select 1 and 0
Select the clock to be input to CMCNT from four internal
clocks obtained by dividing the peripheral operating
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. If the flag is set by another compare match before writing 0 to the bit after reading it as
1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again
and write 0 to it.
Rev. 3.00 May 17, 2007 Page 978 of 1582
REJ09B0181-0300