SH7080 Datasheet, PDF (1603/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
7.4.6 PC Trace
162 Amended
3. BRSR and BRDR have four pairs of queue
structures (eight pairs for the F-ZTAT version
supporting full functions of E10A). The top of queues
is read first when the address stored in the PC trace
register is read. ….
4. Since four pairs (eight pairs for the F-ZTAT version
supporting full functions of E10A) of queue are
shared with the AUD, set the PCTE bit in BRCR to 1
after setting the MSTP25 bit in STBCR5 to 0 and the
AUDSRST bit in STBCR6 to 1. ….
7.5 Usage Notes
169 Added
9. When the DTC or DMAC is in operation, the UBC
cannot correctly determine access to the external
space by the CPU via the I bus. To determine access
to the external space via the I bus in the above
situation, select all bus masters. This makes it
impossible to determine conditions of access with
specified bus masters. However, when a bus master
can be inferred from data values, the relevant data
values can be included as a condition that indicates a
particular bus master.
Figure 8.15 Example of DTC
203
Operation Timing:
Normal or Repeat Transfer
(Activated by IRQ; Iφ: Bφ: Pφ =1:
1/2: 1/2; Data Transferred from
On-Chip Peripheral Module to On-
Chip RAM; Transfer Information is
Written in 3 Cycles)
Added
8.5.9 DTC Bus Release Timing 206 Amended
The DTC requests the bus mastership to the bus arbiter
when an activation request occurs. The DTC releases
the bus after a vector read, NOP cycle generation after
a vector read, transfer information read, a single data
transfer, or transfer information writeback. The DTC
does not release the bus mastership during transfer
information read, single data transfer, or transfer
information writeback.
Rev. 3.00 May 17, 2007 Page 1545 of 1582
REJ09B0181-0300