SH7080 Datasheet, PDF (101/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.5.2 Data Transfer Instructions
Table 2.11 Data Transfer Instructions
Instruction
Operation
Code
MOV #imm,Rn
imm → Sign extension
→ Rn
1110nnnniiiiiiii
MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign
extension → Rn
1001nnnndddddddd
MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn
1101nnnndddddddd
MOV Rm,Rn
Rm → Rn
0110nnnnmmmm0011
MOV.B Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0000
MOV.W Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0001
MOV.L Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0010
MOV.B @Rm,Rn
(Rm) → Sign extension
→ Rn
0110nnnnmmmm0000
MOV.W @Rm,Rn
(Rm) → Sign extension
→ Rn
0110nnnnmmmm0001
MOV.L @Rm,Rn
(Rm) → Rn
0110nnnnmmmm0010
MOV.B Rm,@–Rn
Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100
MOV.W Rm,@–Rn
Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101
MOV.L Rm,@–Rn
Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110
MOV.B @Rm+,Rn
(Rm) → Sign extension
→ Rn, Rm + 1 → Rm
0110nnnnmmmm0100
MOV.W @Rm+,Rn
(Rm) → Sign extension
→ Rn, Rm + 2 → Rm
0110nnnnmmmm0101
MOV.L @Rm+,Rn
(Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110
MOV.B R0,@(disp,Rn) R0 → (disp + Rn)
10000000nnnndddd
MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn)
10000001nnnndddd
MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn)
0001nnnnmmmmdddd
MOV.B @(disp,Rm),R0 (disp + Rm) → Sign
extension → R0
10000100mmmmdddd
MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign
extension → R0
10000101mmmmdddd
MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn
0101nnnnmmmmdddd
Execution
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T Bit
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Rev. 3.00 May 17, 2007 Page 43 of 1582
REJ09B0181-0300