SH7080 Datasheet, PDF (755/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 Port Output Enable (POE)
Bit Bit Name
Initial
value R/W Description
0
MTU2CH34HIZ 0
R/W MTU2 Channel 3 and 4 Output High-Impedance
This bit specifies whether to place the high-current
pins for the MTU2 in high-impedance state.
0: Does not place the pins in high-impedance state
[Clearing conditions]
• Power-on reset
• By writing 0 to MTU2CH34HIZ after reading
MTU2CH34HIZ = 1
1: Places the pins in high-impedance state
[Setting condition]
• By writing 1 to MTU2CH34HIZ
13.3.7 Port Output Enable Control Register 1 (POECR1)
POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
MTU2 MTU2 MTU2 MTU2
PE3ZE PE2ZE PE1ZE PE0ZE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W* R/W* R/W* R/W*
Note: * Can be modified only once after a power-on reset.
Bit
Bit Name
7 to 4 —
Initial
value
All 0
3
MTU2PE3ZE 0
R/W
R
R/W*
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MTU2 PE3 High-Impedance Enable
This bit specifies whether to place the PE3/TIOC0D
pin for channel 0 in the MTU2 in high-impedance
state when either POE8F or MTU2CH0HIZ bit is set
to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
Rev. 3.00 May 17, 2007 Page 697 of 1582
REJ09B0181-0300