SH7080 Datasheet, PDF (1612/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
16.3.7 Serial Status Register
(SCFSR)
Page Revision (See Manual for Details)
805, Amended
809
Bit Bit Name Description
5 TDFE
Transmit FIFO Data Empty
….
1: The number of transmit data in SCFTDR is less
than or equal to the specified transmission
trigger number*
[Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the number of transmit
data in SCFTDR becomes less than or equal
to the specified transmission trigger number
as a result of transmission
0 DR
Receive Data Ready
….
[Clearing conditions]
• DR is cleared to 0 when the chip undergoes a
power-on reset
• DR is cleared to 0 when all receive data are
read after 1 is read from DR and then 0 is
written
• DR is cleared to 0 when all receive data in
SCFRDR are read by the DTC
Figure 16.13 Sample Flowchart for 845
Transmitting Serial Data
Amended
Start of transmission
[1] SCIF status check and transmit data
Read TDFE flag in SCFSR
write:
[1]
Read SCFSR and check that the
No
TDFE = 1?
TDFE flag and the TEND flag are set
to 1, then write transmit data to
SCFTDR, and clear the TDFE flag
Yes
and the TEND flag to 0.
Write transmit data to SCFTDR
and clear TDFE flag
[2] Serial transmission continuation
procedure:
and TEND flag in SCFSR to 0
To continue serial transmission, read
after reading them as 1
1 from the TDFE flag to confirm that
writing is possible, them write data to
SCFTDR, and then clear the TDFE
flag to 0.
Rev. 3.00 May 17, 2007 Page 1554 of 1582
REJ09B0181-0300