SH7080 Datasheet, PDF (460/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
To output a transfer request signal from an on-chip peripheral module, set the interrupt enable bit
corresponding to the transfer request signal in the on-chip peripheral module.
When an interrupt request signal in an on-chip peripheral module is used to request DMA transfer,
no interrupt is requested to the CPU. For details, refer to section 6.8, Data Transfer with Interrupt
Request Signals.
The transfer request signal shown in table 10.7 is automatically cancelled when the corresponding
DMA transfer is performed. This cancellation occurs when one transfer unit is completed in cycle
steal mode or at the end of burst transfer in burst mode.
10.4.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it transfers
data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are
selected by the bits PR1 and PR0 in DMAOR.
(1) Fixed Mode
In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed
modes as follows:
• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1
These are selected by the PR1 and the PR0 bits in DMAOR.
(2) Round-Robin Mode
In round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is
transferred on one channel, the priority is rotated. The channel on which the transfer was just
finished rotates to the bottom of the priority. The round-robin mode operation is shown in figure
10.3. The priority of round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after reset.
When round-robin mode is specified, do not mix the cycle steal mode and the burst mode in
multiple channels' bus modes.
Rev. 3.00 May 17, 2007 Page 402 of 1582
REJ09B0181-0300