SH7080 Datasheet, PDF (100/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
The instruction code, operation, and execution cycles of the instructions are listed in the following
tables, classified by type.
Instruction
Instruction Code
Summary of
Operation
Execution
Cycles T Bit
Indicated by mnemonic. Indicated in MSB ↔
LSB order.
Indicates summary of
operation.
Value when no Value of T bit after
wait cycles are instruction is executed
inserted^*1
Explanation of Symbols
Explanation of Symbols Explanation of Symbols Explanation of Symbols
: No change
OP.Sz SRC, DEST
mmmm: Source register →, ←: Transfer direction
OP: Operation code _{nnnn: Destination}
Sz: Size
register
SRC: Source
0000: R0
DEST: Destination
0001: R1
Rm: Source register
.........
(xx): Memory operand
M/Q/T: Flag bits in SR
&: Logical AND of each bit
|: Logical OR of each bit
Rn: Destination
1111: R15
^: Exclusive logical OR of
register
iiii: Immediate data
each bit
imm: Immediate data dddd: Displacement _{–: Logical NOT of each bit}
disp: Displacement*²
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
• When there is contention between an instruction fetch and a data access
• When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc.
For details, see SH-1/SH-2/SH-DSP Software Manual.
Rev. 3.00 May 17, 2007 Page 42 of 1582
REJ09B0181-0300