SH7080 Datasheet, PDF (1033/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Compare Match Timer (CMT)
Section 20 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The
CMT has a16-bit counter, and can generate interrupts at set intervals.
20.1 Features
• Selection of four counter input clocks
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently
for each channel.
• Interrupt request on compare match
• Module standby mode can be set.
Figure 20.1 shows a block diagram of CMT.
CMI0
Pφ/32
Pφ/512
Pφ/8
Pφ/128
Control circuit
Clock selection
CMI1
Pφ/32
Pφ/512
Pφ/8
Pφ/128
Control circuit
Clock selection
Channel 0
Module bus
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
CMT
Compare match timer start register
Compare match timer control/status register
Compare match timer constant register
Compare match counter
Compare match interrupt
Figure 20.1 Block Diagram of CMT
Channel 1
Bus
interface
Internal bus
TIMCMT3A_000020030900
Rev. 3.00 May 17, 2007 Page 975 of 1582
REJ09B0181-0300