SH7080 Datasheet, PDF (243/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
Configuration of transfer information
in normal address mode
Configuration of transfer information
in short address mode
Lower addresses
Start address
0
MRA
1
MRB
2
3
Reserved
(0 write)
SAR
DAR
Chain
transfer
CRA
MRA MRB
CRB
Reserved
(write 0)
SAR
DAR
CRA
CRB
4 bytes
Lower addresses
Start address
0
1
2
3
MRA
SAR
Transfer information for
one round of transfer
(4 longwords)
Chain
transfer
MRB
CRA
MRA
DAR
CRB
SAR
Transfer information for
the 2nd round of transfer
in chain transfer
(4 longwords)
MRB
CRA
DAR
CRB
4 bytes
Transfer information for
one round of transfer
(3 longwords)
Transfer information for
the 2nd round of transfer
in chain transfer
(3 longwords)
Note: Since the upper 8 bits of SAR and DAR are regarded as all 1,
short address mode can be set only for transfer
between on-chip peripheral modules and on-chip RAM.
Figure 8.2 Transfer Information on Data Area
Upper: DTCVBR
Lower: H'400 + vector number × 4 _{Vector table}
DTC vector
address
+4
+4n
Transfer information (1)
start address
Transfer information (2)
start address
:
:
:
Transfer information (n)
start address
4 bytes
Transfer information (1)
Transfer information (2)
:
:
:
Transfer information (n)
Figure 8.3 Correspondence between DTC Vector Address and Transfer Information
Rev. 3.00 May 17, 2007 Page 185 of 1582
REJ09B0181-0300