SH7080 Datasheet, PDF (30/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figure 9.14 Example of 32-Bit Data Width SDRAM Connection
(RASU and CASU are not Used) ............................................................................ 302
Figure 9.15 Example of 16-Bit Data Width SDRAM Connection
(RASU and CASU are not Used) ............................................................................ 303
Figure 9.16 Example of 16-Bit Data Width SDRAM Connection
(RASU and CASU are Used) .................................................................................. 304
Figure 9.17 Burst Read Basic Timing (Auto-Precharge)............................................................ 318
Figure 9.18 Burst Read Wait Specification Timing (Auto-Precharge)....................................... 319
Figure 9.19 Single Read Basic Timing (Auto-Precharge) .......................................................... 320
Figure 9.20 Basic Timing for SDRAM Burst Write (Auto-Precharge) ...................................... 322
Figure 9.21 Single Write Basic Timing (Auto-Precharge) ......................................................... 323
Figure 9.22 Burst Read Timing (No Auto-Precharge)................................................................ 325
Figure 9.23 Burst Read Timing (Bank Active, Same Row Address) ......................................... 326
Figure 9.24 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 327
Figure 9.25 Single Write Timing (No Auto-Precharge) ............................................................. 328
Figure 9.26 Single Write Timing (Bank Active, Same Row Address)....................................... 329
Figure 9.27 Single Write Timing (Bank Active, Different Row Addresses).............................. 330
Figure 9.28 Auto-Refresh Timing .............................................................................................. 332
Figure 9.29 Self-Refresh Timing ................................................................................................ 333
Figure 9.30 SDRAM Mode Register Write Timing (Based on JEDEC) .................................... 336
Figure 9.31 Burst ROM (Clock Asynchronous) Access
(Bus Width = 32 Bits, 16 byte Transfer (Number of Burst = 4),
Access Wait for the 1st time = 2, Access Wait for 2nd Time and after = 1) ........... 339
Figure 9.32 Basic Access Timing for SRAM with Byte Selection (BAS = 0) ........................... 340
Figure 9.33 Basic Access Timing for SRAM with Byte Selection (BAS = 1) ........................... 341
Figure 9.34 Byte Selection SRAM Wait Timing
(BAS = 1, SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01).................................... 342
Figure 9.35 Example of Connection with 32-Bit Data Width Byte-Selection SRAM................ 343
Figure 9.36 Example of Connection with 16-Bit Data Width Byte-Selection SRAM................ 343
Figure 9.37 Example of PCMCIA Interface Connection............................................................ 345
Figure 9.38 Basic Access Timing for PCMCIA Memory Card Interface................................... 346
Figure 9.39 Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Hardware Wait = 1).............................. 347
Figure 9.40 Example of PCMCIA Space Assignment
(CS5WCR.SA[1:0] = B'10, CS6WCR.SA[1:0] = B'10).......................................... 348
Figure 9.41 Basic Timing for PCMCIA I/O Card Interface ....................................................... 349
Figure 9.42 Wait Timing for PCMCIA I/O Card Interface Timing
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Hardware Wait 1) ................................. 350
Figure 9.43 Burst MPX Device Connection Example................................................................ 351
Figure 9.44 Burst MPX Space Access Timing (Single Read, No Wait or Software Wait 1) ..... 352
Rev. 3.00 May 17, 2007 Page xxx of Iviii