SH7080 Datasheet, PDF (470/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
• Burst Mode
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed
continuously without releasing the bus mastership until the transfer end condition is satisfied.
In external request mode with level detection of the DREQ pin, however, when the DREQ pin
is not active, the bus mastership passes to the other bus master after the DMAC transfer
request that has already been accepted ends, even if the transfer end conditions have not been
satisfied.
Figure 10.12 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read Write Read Write Read Write
Figure 10.12 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
Rev. 3.00 May 17, 2007 Page 412 of 1582
REJ09B0181-0300