SH7080 Datasheet, PDF (983/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
RDRF
9
1
2
3
4
5
6
7
8
9
A
A/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RCVD
ICDRS Data n-1
Data n
ICDRR
User
processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[6] Issue stop [7] Read ICDRR,
condition
and clear RCVD
[8] Set slave
receive mode
Figure 18.8 Master Receive Mode Operation Timing (2)
Rev. 3.00 May 17, 2007 Page 925 of 1582
REJ09B0181-0300