SH7080 Datasheet, PDF (829/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
Receiving Serial Data (Clock Synchronous Mode): Figure 15.12 shows a sample flowchart for
receiving serial data. Use the following procedure for serial data reception after enabling the SCIF
for reception.
When switching from asynchronous mode to clock synchronous mode, make sure that the ORER,
PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not
be set and data reception cannot be started.
Start of reception
Read ORER flag in SCSSR
ORER = 1?
Yes
No
Error handling
Read RDRF flag in SCSSR
No
RDRF = 1?
Yes
Read receive data in SCRDR,
and clear RDRF flag
in SCSSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
[1] Receive error handling:
Read the ORER flag in SCSSR to
identify any error, perform the appropriate
error handling, then clear the ORER flag
to 0. Reception cannot be resumed while
the ORER flag is set to 1.
[2] SCI status check and receive data read:
Read SCSSR and check that RDRF = 1,
then read the receive data in SCRDR,
and clear the RDRF flag to 0. The
transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
[3] Serial reception continuation procedure:
To continue serial reception, read the
receive data register (SCRDR) and clear
the RDRF flag to 0 before the MSB (bit 7)
of the current frame is received. The
RDRF flag is cleared automatically when
the direct memory access controller
(DMAC) or data transfer controller (DTC)
is activated by a receive-data-full interrupt
(RXI) request to read the SCRDR value,
and this step is not needed.
End of reception
Figure 15.12 Sample Flowchart for Receiving Serial Data (1)
Rev. 3.00 May 17, 2007 Page 771 of 1582
REJ09B0181-0300