SH7080 Datasheet, PDF (142/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
4.7 Function for Detecting Oscillator Stop
This CPG detects a stop in the clock input if any system abnormality halts the clock supply.
When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in
OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or
software standby mode is canceled. If the OSCERS bit is set to 1 at this time, an oscillation stop
detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (pins
to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2 and the TIOC3BS,
TIOC3DS, and TIOC4AS to TIOC4DS signals in the MTU2S are assigned) can be placed in high-
impedance state regardless of the PFC setting. For details, refer to section 21.1.11, High-Current
Port Control Register (HCPCR), and appendix A, Pin States.
Even in software standby mode, these pins can be placed in high-impedance state. For details,
refer to section 21.1.11, High-Current Port Control Register (HCPCR), and appendix A, Pin
States. These pins enter the normal state after software standby mode is canceled. Under an
abnormal condition where oscillation stops while the LSI is not in software standby mode, LSI
operations other than the oscillation stop detection function become unpredictable. In this case,
even after oscillation is restarted, LSI operations including the above high-current pins become
unpredictable.
Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues
oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and
operating voltage).
Rev. 3.00 May 17, 2007 Page 84 of 1582
REJ09B0181-0300