SH7080 Datasheet, PDF (43/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figure 28.14 Basic Bus Timing for Normal Space
(One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0),
No Idle Cycle) ..................................................................................................... 1424
Figure 28.15 CS Extended Bus Cycle for Normal Space
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle)................................. 1425
Figure 28.16 Bus Cycle of SRAM with Byte Selection
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle, BAS = 0
(UB/LB in Write Cycle Controlled))................................................................... 1426
Figure 28.17 Bus Cycle of SRAM with Byte Selection
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle, BAS = 1
(WE in Write Cycle Controlled)) ........................................................................ 1427
Figure 28.18 MPX-I/O Interface Bus Cycle
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) .. 1428
Figure 28.19 Burst MPX-I/O Interface Bus Cycle Single Read Write
(One Address Cycle, One Software Wait Cycle) ................................................ 1429
Figure 28.20 Burst MPX-I/O Interface Bus Cycle Single Read Write
(One Address Cycle, One Software Wait Cycle, One External Wait Cycle) ...... 1430
Figure 28.21 Burst MPX-I/O Interface Bus Cycle Burst Read Write
(One Address Cycle, One Software Wait Cycle) ................................................ 1431
Figure 28.22 Burst MPX-I/O Interface Bus Cycle Burst Read Write
(One Address Cycle, One Software Wait Cycle, External Wait Cycle) .............. 1432
Figure 28.23 Burst ROM Read Cycle
(One Software Wait Cycle, One External Wait Cycle, One Burst Wait Cycle,
Two Bursts) ......................................................................................................... 1433
Figure 28.24 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)......... 1434
Figure 28.25 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)......... 1435
Figure 28.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)......... 1436
Figure 28.27 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)......... 1437
Figure 28.28 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 1 Cycle)................................................................... 1438
Figure 28.29 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) ................................. 1439
Figure 28.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle)................................... 1440
Figure 28.31 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)................................... 1441
Rev. 3.00 May 17, 2007 Page xliii of Iviii