SH7080 Datasheet, PDF (84/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
Bit
Read/
Bit
name Default
Write Description
1
S
Undefined R/W S Bit
Used by the multiply and accumulate instruction.
0
T
Undefined R/W T Bit
Indicates true (1) or false (0) in the following
instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S),
BF (BF/S), SETT, CLRT
Indicates carry, borrow, overflow, or underflow in the
following instructions: ADDV, ADDC, SUBV, SUBC,
NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,
SHLL, ROTR, ROTL, ROTCR, ROTCL
• Global-base register (GBR)
This register indicates a base address in GBR indirect addressing mode. The GBR indirect
addressing mode is used for data transfer of the on-chip peripheral module registers and logic
operations.
• Vector-base register (VBR)
This register indicates the base address of the exception handling vector table.
Rev. 3.00 May 17, 2007 Page 26 of 1582
REJ09B0181-0300