SH7080 Datasheet, PDF (1622/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Table 21.22 Transmit Forms of
Input Functions Allocated to
Multiple Pins
Page Revision (See Manual for Details)
1160 Amended
OR Type
AND Type
SCK0, SCK3, RXD0, RXD3,
POE4 to POE8, AUDMD,
TIOC3AS to TIOC3DS,
TIOC4AS to TIOC4DS,
TIC5U, TIC5V, TIC5W,
TIC5US, TIC5VS, TIC5WS
IRQ0 to IRQ7,
DREQ0, DREQ1,
BREQ, WAIT,
ADTRG, AUDRST,
POE4 to POE8
21.2 Usage Notes
Figure 22.9 Port D (SH7083,
SH7084)
Figure 22.10 Port D (SH7085,
SH7086)
Figure 22.11 Port E (SH7083)
Figure 22.12 Port E (SH7084)
Figure 22.13 Port E (SH7085)
Figure 22.14 Port E (SH7086)
Figure 22.13 Port E (SH7085)
1160 Added
4. PFC setting in single-chip mode (MCU operating
mode 3)
In single-chip mode, do not set the PFC to select
address bus, data bus, bus control, or the BREQ,
BACK, CK, DACK, or TEND signals. If they are
selected, address bus signals function as high- or
low-level outputs, data bus signals function as high-
impedance outputs, and the other output signals
function as high-level outputs. As BREQ and WAIT
function as inputs, do not leave them open.
However, the bus-mastership-request inputs and
external waits are disabled.
1191 Deleted
PD13 (I/O)/D13 (I/O)/TIOC4BS (I/O)/AUDMD (input) *
PD12 (I/O)/D12 (I/O)/TIOC4AS (I/O)/AUDRST (input) *
1192 Deleted
PD21 (I/O)/D21 (I/O)/IRQ5 (input)/TIC5VS (input)/
AUDMD (input) *
PD20 (I/O)/D20 (I/O)/IRQ4 (input)/TIC5WS (input)/
AUDRST (input) *
1199 Added
to _{Note: * Only in F-ZTAT version.}
1202
1201 Deleted
PE2 (I/O)/DREQ1 (input)/TIOC0C (I/O)/
AUDRST (input) *
PE1 (I/O)/TEND0 (output)/TIOC0B (I/O)/
AUDMD (input) *
Rev. 3.00 May 17, 2007 Page 1564 of 1582
REJ09B0181-0300