SH7080 Datasheet, PDF (1002/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.8.4 Settings for Multi-Master Operation
1. Transfer rate setting
In multi-master operation, specify a transfer rate of at least 1/1.8 of the fastest transfer rate
among the other masters. For example, when the fastest of the other masters is at 400 kbps, the
IIC transfer rate of this LSI must be specified as 223 kbps (= 400/1.8) or a higher rate.
2. MST and TRS bits in ICCR1
In multi-master operation, use the MOV instruction to set the MST and TRS bits in ICCR1.
3. Loss of arbitration
When arbitration is lost, check whether the MST and TRS bits in ICCR1 are 0. If the MST and
TRS bits in ICCR1 have been set to a value other than 0, clear the bits to 0.
18.8.5 Reading ICDRR in Master Receive Mode
In master receive mode, read ICDRR before the rising edge of the 8th clock of SCL. If ICDRR
cannot be read before the rising edge of the 8th clock so that the next round of reception proceeds
with the RDRF bit in ICSR set to 1, the 8the clock is fixed low and the 9th clock is output.
If ICDRR cannot be read before the rising edge of the 8th clock of SCL, set the RCVD bit in
ICRR1 to 1 so that transfer proceeds in byte units.
Rev. 3.00 May 17, 2007 Page 944 of 1582
REJ09B0181-0300