SH7080 Datasheet, PDF (439/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
takes (1 + n) × Iφ (n = 0 to 1) (2 × Iφ is indicated in figure 9.54). The relation between the timing
of data output to the L bus and the rising edge of Bφ depends on the state of program execution.
Data output to the I bus are transferred to the external bus after one cycle of Bφ. External access to
each data takes at least two cycles, and this can be prolonged by the BSC register settings (m and
o in the formulae for number of access cycles). In the case shown in figure 9.54, word data is
written with a bus-width of 8 bits, two external accesses are required. In the example, since n = 1,
m = 0, and o = 0, access takes 2 × Iφ + 3 × Bφ + 2 × Bφ.
Iφ
L bus
Bφ (CK)
I bus
External bus
First external access Second external access
(1 + n) × Iφ
This access period is
This access period is
prolonged by a period of m. prolonged by a period of o.
(3 + m) × Bφ
(2 + o) × Bφ
In this example, m = 0 and o = 0.
For the numbers of cycles by which
m and o prolong the access process,
see section 9.4, Register Descriptions.
Figure 9.54 Timing of Write Access to Word Data in External Memory
When Iφ:Bφ = 2:1 and External Bus Width is 8 Bits
Figure 9.55 shows an example of the timing of read access when the external bus width is greater
than or equal to the data width and Iφ:Bφ = 4:1. Transfer from the L bus to the external bus is
performed in the same way as for write access. In the case of reading, however, values output onto
the external bus must be transferred to the CPU. Transfers from the external bus to the I bus and
from the I bus to the L bus are again performed in synchronization with rising edges of the
respective bus clocks. In the actual operation, transfer from the external bus to the L bus takes one
φ period. In the case shown in the figure, where n = 2 and m = 0, access takes 3 × Iφ + 3 × Bφ + 1
× Iφ.
Rev. 3.00 May 17, 2007 Page 381 of 1582
REJ09B0181-0300