SH7080 Datasheet, PDF (227/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7. User breaks are disabled during UBC module standby mode. Do not read from or write to the
UBC registers during UBC module standby mode; the values are not guaranteed.
8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a
SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a
SLEEP instruction or one or two instructions before a SLEEP instruction.
9. When the DTC or DMAC is in operation, the UBC cannot correctly determine access to the
external space by the CPU via the I bus. To determine access to the external space via the I bus
in the above situation, select all bus masters. This makes it impossible to determine conditions
of access with specified bus masters. However, when a bus master can be inferred from data
values, the relevant data values can be included as a condition that indicates a particular bus
master.
Rev. 3.00 May 17, 2007 Page 169 of 1582
REJ09B0181-0300