SH7080 Datasheet, PDF (442/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip peripheral
module
DTC
CPU/DTC/DMAC
request
distinguish
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
DEIn
Iteration
control
Register
control
Start-up
control
Request
priority
control
DMAC module
SARn
DARn
DMATCRn
CHCRn
DMAOR
External
memory
External
I/O (memory
mapped)
External
I/O (with
acknowledge)
DACK0 to DACK3,
TEND0, TEND1
DREQ0 to DREQ3
Bus
interface
Bus state
controller
[Legend]
SARn:
DMA source address register
DARn:
DMA destination address register
DMATCRn: DMA transfer count register
CHCRn: DMA channel control register
DMAOR: DMA operation register
DEIn:
DMA transfer-end interrupt request to the CPU
n:
0, 1, 2, 3
Figure 10.1 Block Diagram of DMAC
Rev. 3.00 May 17, 2007 Page 384 of 1582
REJ09B0181-0300