SH7080 Datasheet, PDF (399/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
T1
T2
CK
A29 to A0
CSn
WRxx
RDWR
Read
RD
D31 to D0
RDWR
Write
RD
D31 to D0
High
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.33 Basic Access Timing for SRAM with Byte Selection (BAS = 1)
Rev. 3.00 May 17, 2007 Page 341 of 1582
REJ09B0181-0300