SH7080 Datasheet, PDF (1611/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
15.3.8 Serial Port Register
(SCSPTR)
Page Revision (See Manual for Details)
741 Amended
Bit Bit Name Description
1 SPB0IO Serial Port Break Output
Together with the SPB0DT bit and the TE bit in
SCSCR, controls the TXD pin.
0 SPB0DT Serial Port Break Data
Together with the SPB0IO bit and TE bit in
SCSCR, controls the TXD pin. Note that the TXD
pin function needs to have been selected with the
pin function controller (PFC).
TE bit SPB0IO SPB0DT
setting in bit
bit
SCSCR setting setting State of TXD pin
0
0
*
SPB0DT output
disabled
(initial state)
0
1
0
Output, low level
0
1
1
Output, high level
1
*
*
Output for transmit
data in accord with
the serial core logic
Note: * Don't care
15.4.3 Clock Synchronous Mode 767
Added
(2) Clock
Eight clock pulses are output per transmitted or
received character. When the SCI does not perform
transmission or reception, the clock signal remains in
the high state. When only reception is performed, output
of the synchronous clock continues until an overrun
error occurs or the RE bit is cleared to 0. For the
reception of n characters, select the external clock as
the clock source. If the internal clock has to be used, set
RE and TE to 1, then transmit n characters of dummy
data at the same time as receiving the n characters of
data.
Rev. 3.00 May 17, 2007 Page 1553 of 1582
REJ09B0181-0300