SH7080 Datasheet, PDF (17/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

11.7.2 Input Clock Restrictions ....................................................................................... 623
11.7.3 Caution on Period Setting ..................................................................................... 624
11.7.4 Contention between TCNT Write and Clear Operations...................................... 624
11.7.5 Contention between TCNT Write and Increment Operations............................... 625
11.7.6 Contention between TGR Write and Compare Match .......................................... 626
11.7.7 Contention between Buffer Register Write and Compare Match ......................... 627
11.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 628
11.7.9 Contention between TGR Read and Input Capture............................................... 629
11.7.10 Contention between TGR Write and Input Capture.............................................. 630
11.7.11 Contention between Buffer Register Write and Input Capture ............................. 631
11.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 631
11.7.13 Counter Value during Complementary PWM Mode Stop .................................... 633
11.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 633
11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 634
11.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 635
11.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 636
11.7.18 Contention between TCNT Write and Overflow/Underflow................................ 637
11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1
to Reset-Synchronized PWM Mode ..................................................................... 637
11.7.20 Output Level in Complementary PWM Mode
and Reset-Synchronized PWM Mode................................................................... 638
11.7.21 Interrupts in Module Standby Mode ..................................................................... 638
11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 638
11.8 MTU2 Output Pin Initialization......................................................................................... 639
11.8.1 Operating Modes................................................................................................... 639
11.8.2 Reset Start Operation ............................................................................................ 639
11.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc................... 640
11.8.4 Overview of Initialization Procedures and Mode Transitions
in Case of Error during Operation, etc.................................................................. 641
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) ..............................671
12.1 Input/Output Pins ............................................................................................................... 675
12.2 Register Descriptions ......................................................................................................... 676
Section 13 Port Output Enable (POE) ...............................................................679
13.1 Features.............................................................................................................................. 679
13.2 Input/Output Pins ............................................................................................................... 681
13.3 Register Descriptions ......................................................................................................... 683
13.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 684
13.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 688
Rev. 3.00 May 17, 2007 Page xvii of lviii