SH7080 Datasheet, PDF (969/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Bit
2 to 0
Bit Name
BC[2:0]
Initial
Value
000
R/W Description
R/W Bit Counter 2 to 0
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I²C bus format, the data is
transferred with one addition acknowledge bit. Should
be made between transfer frames. If bits BC2 to BC0
are set to a value other than 000, the setting should be
made while the SCL pin is low. The value returns to 000
at the end of a data transfer, including the acknowledge
bit. These bits are automatically set to 111 after a stop
condition is detected. These bits are cleared by a
power-on reset and in standby mode. These bits are
also cleared by setting IICRST of ICCR2 to 1. With the
clock synchronous serial format, these bits should not
be modified.
I²C Bus Format
Clock Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bit
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
Rev. 3.00 May 17, 2007 Page 911 of 1582
REJ09B0181-0300