SH7080 Datasheet, PDF (1011/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 A/D Converter (ADC)
19.3.3 A/D Control Registers_0 to _2 (ADCR_0 to ADCR_2)
ADCR for each module controls A/D conversion.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
- ADST -
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
15, 14 
All 0
13
ADST
0
12 to 0 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W A/D Start
Starts or stops A/D conversion. When this bit is set to
1, A/D conversion is started. When this bit is cleared
to 0, A/D conversion is stopped and the A/D converter
enters the idle state. In single or single-cycle scan
mode, this bit is automatically cleared to 0 when A/D
conversion ends on the selected single channel. In
continuous scan mode, A/D conversion is continuously
performed for the selected channels in sequence until
this bit is cleared by software, reset, or in software
standby mode or module standby mode.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 May 17, 2007 Page 953 of 1582
REJ09B0181-0300