SH7080 Datasheet, PDF (684/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the
compare match signal is also generated.
Figure 11.123 shows the timing in this case.
MPφ
Address
TGR write cycle
T1 T2
TGR address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 11.123 Contention between TGR Write and Compare Match
Rev. 3.00 May 17, 2007 Page 626 of 1582
REJ09B0181-0300