SH7080 Datasheet, PDF (447/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.3.4 DMA Channel Control Registers_0 to _3 (CHCR_0 to CHCR_3)
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
DO TL
-
-
-
-
AM AL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R
R
R
R R/W R/W
Bit: 15 14
DM[1:0]
Initial value: 0
0
R/W: R/W R/W
13 12
SM[1:0]
0
0
R/W R/W
11
0
R/W
10 9
RS[3:0]
0
0
R/W R/W
8
0
R/W
7
DL
0
R/W
6
DS
0
R/W
5
TB
0
R/W
4
3
TS[1:0]
0
0
R/W R/W
2
1
0
IE
TE DE
0
0
0
R/W R/(W)* R/W
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit
Bit Name Value R/W Descriptions
31 to 24 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
23
DO
0
R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22
TL
0
R/W Transfer End Level
This bit specifies the TEND signal output is high active
or low active.
0: Low-active output of TEND
1: High-active output of TEND
21, 20 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
19
—
0
R
Reserved
Undefined value is set when the DMAC is activated.
18
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 389 of 1582
REJ09B0181-0300