SH7080 Datasheet, PDF (982/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Master transmit mode
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
A
TDRE
Master receive mode
1
2
3
4
5
6
7
8
9
1
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
Data 1
User
processing
[1] Clear TDRE after clearing [2] Read ICDRR (dummy read)
TEND and TRS
[3] Read ICDRR
Figure 18.7 Master Receive Mode Operation Timing (1)
Rev. 3.00 May 17, 2007 Page 924 of 1582
REJ09B0181-0300