SH7080 Datasheet, PDF (860/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7 Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR
data, and the lower 8 bits indicate the status flag indicating SCIF operating state.
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written.
Bit: 15 14 13 12 11 10 9
PER[3:0]
FER[3:0]
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
ER TEND TDFE BRK FER PER RDF DR
0
0
1
1
0
0
R R/(W)* R/(W)* R/(W)* R/(W)* R
0
0
0
R R/(W)* R/(W)*
Note: * To clear the flag, only 0 can be written after reading 1.
Bit
Bit Name
15 to 12 PER[3:0]
11 to 8 FER[3:0]
Initial
value
0000
0000
R/W
R
R
Description
Number of Parity Errors
Indicate the number of data including a parity error in
the receive data stored in the receive FIFO data
register (SCFRDR). After the ER bit in SCFSR is set
to 1, the value indicated by bits 15 to 12 indicates the
number of parity errors in SCFRDR. When parity
errors have occurred in all 16-byte receive data in
SCFRDR, PER3 to PER0 show 0.
Number of Framing Errors
Indicate the number of data including a framing error
in the receive data stored in SCFRDR. After the ER
bit in SCFSR is set to 1, the value indicated by bits 11
to 8 indicates the number of framing errors in
SCFRDR. When framing errors have occurred in all
16-byte receive data in SCFRDR, FER3 to FER0
show 0.
Rev. 3.00 May 17, 2007 Page 802 of 1582
REJ09B0181-0300