SH7080 Datasheet, PDF (1606/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
9.4.2 CSn Space Bus Control
Register (CSnBCR) (n = 0 to 8)
Page Revision (See Manual for Details)
247 Added
Bit
Bit Name Description
14 to 12 TYPE[2:0] Memory Type Specification
…….
Notes:2. SDRAM can be selected only for
areas 2 and 3. If the SDRAM is
only to be connected in one area,
select area 3 as the SDRAM
space. In this case, specify area 2
as normal space or SRAM with
byte selection.
9.4.8 Bus Function Extending
Register (BSCEHR)
282
Added
Bit Bit Name Description
9 CSSTP3 Select Priority for External Memory Access by CPU
…….
Note: When this bit is 0, and access to internal I/O
from the CPU is immediately followed by
access to external space from the CPU, a
NOP 1Bφ in duration is inserted between the
two access cycles.
9.5.13 Bus Arbitration
374 Added
When the SDRAM interface is used, an all bank
precharge command (PALL) is issued if any active
banks exist and releases the bus after completion of the
PALL command.
Processing by this LSI continues even while bus
mastership is released to an external device, unless an
external device is accessed. When an external device is
accessed, the LSI enters the state of waiting for bus
mastership to be returned.
376 Added
Acceptance of mastership for the DMAC in bus
arbitration takes 1Bφ, so a NOP 1Bφ in duration is
inserted on the I bus.
Acceptance of mastership for the DTC in bus arbitration
does not require the insertion of a NOP, so bus access
proceeds continuously.
Rev. 3.00 May 17, 2007 Page 1548 of 1582
REJ09B0181-0300