SH7080 Datasheet, PDF (960/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Clock synchronous serial format:
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
The data transfer controller (DTC) can be activated by a transmit-data-empty request or
receive-data-full request to transfer data.
SCL
SDA
Output
control
Noise canceler
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
Address
comparator
NF2CYC
[Legend]
ICCR1 :
ICCR2 :
ICMR :
ICSR :
ICIER :
ICDRT :
ICDRR :
ICDRS :
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus status register
I²C bus interrupt enable register
I²C bus transmit data register
I²C bus receive data register
I²C bus shift register
SAR :
Slave address register
NF2CYC : NF2CYC register
Bus state
decision circuit
Arbitration
decision circuit
ICIER
ICSR
Interrupt
generator
Figure 18.1 Block Diagram of I²C Bus Interface 2
Interrupt
request
Rev. 3.00 May 17, 2007 Page 902 of 1582
REJ09B0181-0300