SH7080 Datasheet, PDF (1507/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

CK
A25 to A0
A12/A11^*1
CSn
RDWR
RASx
CASx
Tp
Tpw
Trr
t_AD1
t_AD1
t_AD1
t_AD1
t_CSD
t_CSD
t_CSD
t_CSD
t_RWD
t_RWD
t_RASD
t_RASD
t_RASD
t_RASD
t_CASD
t_CASD
Section 28 Electrical Characteristics
Trc
Trc
Trc
t_RWD
DQMxx
D31 to D0
(Hi-Z)
BS
CKE
TDEANCDKnn^**22
t_CKED
t_CKED
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.39 Synchronous DRAM Self-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)
Rev. 3.00 May 17, 2007 Page 1449 of 1582
REJ09B0181-0300