SH7080 Datasheet, PDF (48/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.9
Table 5.10
Table 5.11
Calculating Exception Handling Vector Table Addresses...................................... 90
Reset Status............................................................................................................. 91
Bus Cycles and Address Errors............................................................................... 93
Interrupt Sources..................................................................................................... 95
Interrupt Priority ..................................................................................................... 96
Types of Exceptions Triggered by Instructions ...................................................... 97
Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions .............. 99
Stack Status after Exception Handling Ends......................................................... 100
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Configuration.................................................................................................. 107
Table 6.2 Register Configuration.......................................................................................... 108
Table 6.3 Interrupt Exception Handling Vectors and Priorities............................................ 124
Table 6.4 Interrupt Response Time....................................................................................... 131
Section 7 User Break Controller (UBC)
Table 7.1 Pin Configuration.................................................................................................. 137
Table 7.2 Register Configuration.......................................................................................... 138
Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions........... 160
Section 8 Data Transfer Controller (DTC)
Table 8.1 Register Configuration.......................................................................................... 173
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 186
Table 8.3 DTC Transfer Modes ............................................................................................ 189
Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included) ........................ 191
Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped
Registers ............................................................................................................... 195
Table 8.6 Register Function in Normal Transfer Mode........................................................ 195
Table 8.7 Register Function in Repeat Transfer Mode ......................................................... 197
Table 8.8 Register Function in Block Transfer Mode........................................................... 198
Table 8.9 DTC Execution Status .......................................................................................... 204
Table 8.10 Number of Cycles Required for Each Execution State ......................................... 205
Table 8.11 DTC Bus Release Timing ..................................................................................... 207
Section 9 Bus State Controller (BSC)
Table 9.1 Pin Configuration.................................................................................................. 220
Table 9.2 Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM-
Enabled Mode....................................................................................................... 222
Table 9.3 Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM-
Disabled Mode...................................................................................................... 223
Table 9.4 Address Map: SH7083 (512-Kbyte Flash Memory Version) in On-Chip ROM-
Enabled Mode....................................................................................................... 224
Rev. 3.00 May 17, 2007 Page xlviii of Iviii