SH7080 Datasheet, PDF (444/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.3 Register Descriptions
The DMAC has the following registers. See section 27, List of Registers, for the addresses of
these registers and the state of them in each processing status. The SAR for channel 0 is expressed
such as SAR_0.
Table 10.2 Register Configuration
Channel Register Name
Abbrevia-
tion
R/W
0
DMA source
SAR_0
R/W
address register_0
DMA destination DAR_0
R/W
address register_0
DMA transfer count DMATCR_0 R/W
register_0
DMA channel
CHCR_0 R/W
control register_0
1
DMA source
SAR_1
R/W
address register_1
DMA destination DAR_1
R/W
address register_1
DMA transfer count DMATCR_1 R/W
register_1
DMA channel
CHCR_1 R/W
control register_1
2
DMA source
SAR_2
R/W
address register_2
DMA destination DAR_2
R/W
address register_2
DMA transfer count DMATCR_2 R/W
register_2
DMA channel
CHCR_2 R/W
control register_2
Initial value
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
Address
H'FFFFEB20
H'FFFFEB24
H'FFFFEB28
H'FFFFEB2C
H'FFFFEB30
H'FFFFEB34
H'FFFFEB38
H'FFFFEB3C
H'FFFFEB40
H'FFFFEB44
H'FFFFEB48
H'FFFFEB4C
Access Size
16, 32
16, 32
16, 32
8, 16, 32
16, 32
16, 32
16, 32
8, 16, 32
16, 32
16, 32
16, 32
8, 16, 32
Rev. 3.00 May 17, 2007 Page 386 of 1582
REJ09B0181-0300