SH7080 Datasheet, PDF (906/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 16.16 Sample Flowchart for Receiving Serial Data (2)
In receiving, the SCIF operates as follows:
1. The SCIF synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed
(overrun error is detected), further reception is prevented.
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
the SCIF requests a receive-data-full interrupt (RXIF). If the ORER bit is set to 1 and the RIE
bit or REIE bit in SCSCR is also set to 1, the SCIF requests a break interrupt (BRIF).
Figure 16.17 shows an example of SCIF receive operation.
Synchronization
clock
Serial data
LSB
Bit 7 Bit 0
MSB
Bit 7 Bit 0
Bit 1
Bit 6 Bit 7
RDF
ORER
RXIF
interrupt
request
Data read from _RXIF
SCFRDR and _interrupt
RDF flag cleared _request
to 0 by RXIF
interrupt handler
One frame
BRIF interrupt request
by overrun error
Figure 16.17 Example of SCIF Receive Operation
Rev. 3.00 May 17, 2007 Page 848 of 1582
REJ09B0181-0300