SH7080 Datasheet, PDF (111/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
• Reset state
The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the
RES pin is high and MRES pin is low, the CPU enters the manual reset state.
• Exception handling state
This state is a transitional state in which the CPU processing state changes due to a request for
exception handling such as a reset or an interrupt.
When a reset occurs, the execution start address as the initial value of the program counter
(PC) and the initial value of the stack pointer (SP) are fetched from the exception handling
vector table. Then, a branch is made for the start address to execute a program.
When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to
by SP. The start address of an exception handling routine is fetched from the exception
handling vector table and a branch to the address is made to execute a program.
Then the processing state enters the program execution state.
• Program execution state
The CPU executes programs sequentially.
• Power-down state
The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter
sleep mode, software standby mode, or deep software standby mode.
• Bus release state
In the bus release state, the CPU releases access rights to the bus to the device that has
requested them.
Rev. 3.00 May 17, 2007 Page 53 of 1582
REJ09B0181-0300