SH7080 Datasheet, PDF (35/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figure 11.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
with Interrupt Skipping.......................................................................................... 594
Figure 11.83 Example of Synchronous Counter Start Setting Procedure ................................... 595
Figure 11.84 (1) Example of Synchronous Counter Start Operation
(MTU2-to-MTU2S Clock Frequency Ratio = 1:1).......................................... 596
Figure 11.84 (2) Example of Synchronous Counter Start Operation
(MTU2-to-MTU2S Clock Frequency Ratio = 1:2).......................................... 597
Figure 11.84 (3) Example of Synchronous Counter Start Operation
(MTU2-to-MTU2S Clock Frequency Ratio = 1:3).......................................... 597
Figure 11.84 (4) Example of Synchronous Counter Start Operation
(MTU2-to-MTU2S Clock Frequency Ratio = 1:4).......................................... 598
Figure 11.85 Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag
Setting Source.................................................................................................. 599
Figure 11.86 (1) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source
(1)..................................................................................................................... 600
Figure 11.86 (2) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source
(2)..................................................................................................................... 600
Figure 11.87 Example of External Pulse Width Measurement Setting Procedure...................... 601
Figure 11.88 Example of External Pulse Width Measurement
(Measuring High Pulse Width).............................................................................. 601
Figure 11.89 Delay in Dead Time in Complementary PWM Operation..................................... 602
Figure 11.90 Example of Dead Time Compensation Setting Procedure .................................... 603
Figure 11.91 Example of Motor Control Circuit Configuration ................................................. 603
Figure 11.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation..... 604
Figure 11.93 Count Timing in Internal Clock Operation (Channels 0 to 4) ............................... 610
Figure 11.94 Count Timing in Internal Clock Operation (Channel 5)........................................ 610
Figure 11.95 Count Timing in External Clock Operation (Channels 0 to 4) .............................. 610
Figure 11.96 Count Timing in External Clock Operation (Phase Counting Mode).................... 611
Figure 11.97 Output Compare Output Timing (Normal Mode/PWM Mode)............................. 611
Figure 11.98 Output Compare Output Timing
(Complementary PWM Mode/Reset Synchronous PWM Mode) ......................... 612
Figure 11.99 Input Capture Input Signal Timing........................................................................ 612
Figure 11.100 Counter Clear Timing (Compare Match) (Channels 0 to 4) ................................ 613
Figure 11.101 Counter Clear Timing (Compare Match) (Channel 5)......................................... 613
Figure 11.102 Counter Clear Timing (Input Capture) (Channels 0 to 5).................................... 614
Figure 11.103 Buffer Operation Timing (Compare Match)........................................................ 614
Figure 11.104 Buffer Operation Timing (Input Capture) ........................................................... 614
Figure 11.105 Buffer Transfer Timing (when TCNT Cleared) .................................................. 615
Figure 11.106 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) ... 615
Rev. 3.00 May 17, 2007 Page xxxv of Iviii