SH7080 Datasheet, PDF (1598/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Figure 1.6 Pin Assignments of
SH7083 (P-LFBGA-112)
Table 1.2 Pin Functions
Page Revision (See Manual for Details)
12 Added
21, Amended
22
Classification
Symbol Function
User debugging
interface (H-UDI)
(only in the F-ZTAT
version)
E10A interface
(only in the F-ZTAT
version)
TCK
Test-clock input pin.
ASEMD0 Sets the ASE mode.
21 Deleted
Classification
Symbol
I/O Name
Function
Advanced user AUDATA3 to O
debugger (AUD) AUDATA0
(only in F-ZTAT _AUDRST
I
version supporting
full functions of ^AUDMD
I
E10A)
AUD data Branch destination
address output pins.
AUD reset Reset signal input pin.
AUD mode Low-level input when the
AUD function is used.
Figure 3.1 Address Map for Each 58,
Operating Mode in SH7083
59
(256-Kbyte Flash Memory
Version)
Figure 3.2 Address Map for Each
Operating Mode in SH7083
(512-Kbyte Flash Memory
Version)
Table 4.4 Frequency Division
76
Ratios Specifiable with FRQCR
Amended
Amended
Notes: 2. The output frequency of the PLL circuit is the
product of the frequency of the input from the
crystal resonator or EXTAL pin and the
multiplication ratio (×8) of the PLL circuit. This
output frequency must be 80 MHz or lower.
7. …….The MTU2 clock (MPφ) frequency must
be equal to or lower than the MTU2S clock
(MIφ) frequency and the bus clock (Bφ)
frequency and equal to or higher than the
peripheral clock frequency (Pφ).
Rev. 3.00 May 17, 2007 Page 1540 of 1582
REJ09B0181-0300