SH7080 Datasheet, PDF (914/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
Base clock
–7.5 clocks
+7.5 clocks
Receive data
(RXD)
Synchronization
sampling timing
Start bit
D0
D1
Data sampling
timing
Figure 16.23 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5 - ¹ ) - (L - 0.5) F - ^{D - 0.5} (1+F) × 100 %
2N
N
Where: M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M
= (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 3.00 May 17, 2007 Page 856 of 1582
REJ09B0181-0300