SH7080 Datasheet, PDF (1613/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
Figure 16.18 Sample Flowchart for 849
Transmitting/Receiving Serial
Data
Amended
Initialization
Start of transmission and reception
Read TDFE flag in SCFSR
[1]
No
TDFE = 1?
Yes
Write transmit data to SCFTDR,
and clear TDFE flag
and TEND flag in SCFSR to 0
after reading them as 1
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag and the TEND flag are set
to 1, then write transmit data to
SCFTDR, and clear the TDFE flag
and the TEND flag to 0. The transition
of the TDFE flag from 0 to 1 can also
be identified by a TXIF interrupt.
[2] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be
resumed while the ORER flag is set
to 1.
16.7.8 FER Flag and PER Flag of 857
Serial Status Register (SCFSR)
17.3.6 SS Control Register 2
872
(SSCR2)
Added
Amended
SSCR2 is a register that enables/disables the open-
drain outputs of the SSO, SSI, SSCK, and SCS pins,
selects the assert timing of the SCS pin, data output
timing of the SSO pin, and set timing of the TEND bit.
Initial
Bit Bit Name Value R/W Description
7 to 5 
All 0 R
Reserved
These bits are always read as 0.
The write value should always be 0.
Table 17.6 Communication Modes 880
and Pin States of SSCK Pin
Deleted
Communication ^{Register Setting}
Mode
MSS
SCKS
SSU
0
0
communication
1
mode
1
0
1
Clock
0
0
synchronous
1
communication
mode
1
0
1
Pin State
SSCK
Input
Output
Input
Output
Rev. 3.00 May 17, 2007 Page 1555 of 1582
REJ09B0181-0300