SH7080 Datasheet, PDF (1602/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
7.3.10 Break Bus Cycle Register 148, Amended
B (BBRB)
149 _{Bit Bit Name Description}
10 CPB2* Bus Master Select B for I Bus
9 CPB1*
8 CPB0*
7 CDB1* L Bus Cycle/I Bus Cycle Select B
6 CDB0
5 IDB1*
4 IDB0
Instruction Fetch/Data Access
Select B
3 RWB1* Read/Write Select B
2 RWB0
1 SZB1* Operand Size Select B
0 SZB0*
Note: * These bits are reserved in the mask ROM and
ROM-less versions. These bits are always read
as 0. The write value should always be 0.
7.3.13 Branch Source Register 156
(BRSR) (Only in F-ZTAT Version)
Amended
…. This flag bit is cleared to 0 when BRSR is read, the
setting to enable PC trace is made, or BRSR is
initialized by a power-on reset or a manual reset. Other
bits are not initialized by a power-on reset. The four
BRSR registers (eight pairs for the F-ZTAT version
supporting full functions of E10A) have a queue
structure and a stored register is shifted at every
branch.
7.3.14 Branch Destination
157
Register (BRDR) (Only in F-ZTAT
Version)
Amended
…. This flag bit is cleared to 0 when BRDR is read, the
setting to enable PC trace is made, or BRDR is
initialized by a power-on reset or a manual reset. Other
bits are not initialized by a power-on reset. The four
BRSR registers (eight pairs for the F-ZTAT version
supporting full functions of E10A) have a queue
structure and a stored register is shifted at every
branch.
Rev. 3.00 May 17, 2007 Page 1544 of 1582
REJ09B0181-0300