SH7080 Datasheet, PDF (839/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
15.5 SCI Interrupt Sources and DMAC/DTC
The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full
(RXI), and transmit-data-empty (TXI) interrupt requests.
Table 15.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of
the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt
request is generated. This request can be used to activate the direct memory access controller
(DMAC) or data transfer controller (DTC) to transfer data. The TDRE flag is automatically
cleared to 0 when data is written to the transmit data register (SCTDR) through the DMAC or
DTC.
When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. This request
can be used to activate the DMAC or DTC to transfer data. The RDRF flag is automatically
cleared to 0 when data is read from the receive data register (SCRDR) through the DMAC or
DTC.
When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated.
This request cannot be used to activate the DMAC or DTC. When processing the received data
through the DMAC or DTC and handling the receive error by an interrupt requested to the CPU,
set the RIE bit to 1 and set the EIO bit in SCSPTR to 1 to issue an interrupt to the CPU only when
a receive error is detected. If the EIO bit is cleared to 0, an interrupt is issued to the CPU even
when correct data is received.
When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. This request
cannot be used to activate the DMAC or DTC.
The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that
transmission has been completed.
Table 15.17 SCI Interrupt Sources
Interrupt Source Description
DMAC/DTC Activation
ERI
Interrupt caused by receive error (ORER, FER, or Not possible
PER)
RXI
Interrupt caused by receive data full (RDRF)
Possible
TXI
Interrupt caused by transmit data empty (TDRE) Possible
TEI
Interrupt caused by transmit end (TENT)
Not possible
Rev. 3.00 May 17, 2007 Page 781 of 1582
REJ09B0181-0300