SH7080 Datasheet, PDF (229/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by
an interrupt request.
8.1 Features
• Transfer possible over any number of channels:
• Chain transfer
Multiple rounds of data transfer is executed in response to a single activation source
Chain transfer is only possible after data transfer has been done for the specified number of
times (i.e. when the transfer counter is 0)
• Three transfer modes
Normal/repeat/block transfer modes selectable
Transfer source and destination addresses can be selected from increment/decrement/fixed
• The transfer source and destination addresses can be specified by 32 bits to select a 4-Gbyte
address space directly
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC
A CPU interrupt can be requested after one data transfer completion
A CPU interrupt can be requested after the specified data transfer completion
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop mode specifiable
• Short address mode specifiable
• Bus release timing selectable from five types
• Priority of the DTC activation selectable from two types
Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*.
Note: When the transfer information is stored in the on-chip RAM, the RAME bit in RAMCR
must be set to 1.
DTCHX10A_000020030600
Rev. 3.00 May 17, 2007 Page 171 of 1582
REJ09B0181-0300