SH7080 Datasheet, PDF (1230/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 22 I/O Ports
Table 22.2 Port A Data Register (PADR) Read/Write Operations
• PADRH Bits 13 to 0 and PADRL Bits 15 to 0
PAIOR
Pin Function Read
Write
0
General input Pin state
Can write to PADRH and PADRL, but it has no
effect on pin state
Other than
general input
Pin state
Can write to PADRH and PADRL, but it has no
effect on pin state
1
General output PADRH or
Value written is output from pin
PADRL value
Other than
PADRH or
Can write to PADRH and PADRL, but it has no
general output PADRL value effect on pin state
22.1.3 Port A Port Registers H and L (PAPRH and PAPRL)
The port A port registers H and L (PAPRH and PAPRL) are 16-bit read-only registers that always
return the states of the pins regardless of the PFC setting. Bits PA15PR to PA12PR, PA10PR to
PA7PR, and PA5PR to PA3PR correspond to pins PA15 to PA12, PA10 to PA7, and PA5 to PA3,
respectively (multiplexed functions omitted here) in the SH7083. Bits PA17PR to PA0PR
correspond to pins PA17 to PA0 (multiplexed functions omitted here) in the SH7084. Bits
PA25PR to PA0PR correspond to pins PA25 to PA0 (multiplexed functions omitted here) in the
SH7085. Bits PA29PR to PA0PR correspond to pins PA29 to PA0 (multiplexed functions omitted
here) in the SH7086.
• PAPRH (SH7083)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
15 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 1172 of 1582
REJ09B0181-0300