SH7080 Datasheet, PDF (31/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figure 9.45 Burst MPX Space Access Timing
(Single Write, Software Wait 1, Hardware Wait 1)................................................. 353
Figure 9.46 Burst MPX Space Access Timing (Burst Read, No Wait or Software Wait 1) ...... 354
Figure 9.47 Burst MPX Space Access Timing (Burst Write, No Wait) ..................................... 355
Figure 9.48 Burst ROM (Clock Synchronous) Access Timing
(Burst Length = 8, Access Wait for the 1st time = 2,
Access Wait for 2nd Time after = 1) ....................................................................... 356
Figure 9.49 Bus Arbitration when DTC and DMAC Compete during External Space Access
from CPU ................................................................................................................ 371
Figure 9.50 Bus Arbitration when DTC or DMAC Activation Request Occurs during
External Space Access from CPU ........................................................................... 373
Figure 9.51 Bus Arbitration Timing ........................................................................................... 375
Figure 9.52 Timing of Write Access to On-Chip Peripheral I/O Registers
When Iφ:Bφ:Pφ = 4:2:2 ........................................................................................... 379
Figure 9.53 Timing of Read Access to On-Chip Peripheral I/O Registers
When Iφ:Bφ:Pφ = 4:2:1 ........................................................................................... 379
Figure 9.54 Timing of Write Access to Word Data in External Memory
When Iφ:Bφ = 2:1 and External Bus Width is 8 Bits............................................... 381
Figure 9.55 Timing of Read Access with Condition Iφ:Bφ = 4:1
and External Bus Width ≥ Data Width .................................................................... 382
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 Block Diagram of DMAC ....................................................................................... 384
Figure 10.2 DMA Transfer Flowchart ........................................................................................ 398
Figure 10.3 Round-Robin Mode................................................................................................. 403
Figure 10.4 Changes in Channel Priority in Round-Robin Mode............................................... 404
Figure 10.5 Example of Activation Priority Operation of DMAC
(Priority Fixed Mode (CH0 > CH1 > CH2 > CH3))................................................ 405
Figure 10.6 Data Flow of Dual Address Mode........................................................................... 407
Figure 10.7 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)................................. 408
Figure 10.8 Data Flow in Single Address Mode......................................................................... 409
Figure 10.9 Example of DMA Transfer Timing in Single Address Mode.................................. 410
Figure 10.10 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection) ....................................................... 411
Figure 10.11 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection) ....................................................... 411
Figure 10.12 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection) ....................................................... 412
Figure 10.13 Bus State when Multiple Channels are Operating ................................................. 414
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 415
Rev. 3.00 May 17, 2007 Page xxxi of Iviii